Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.

We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a Staff Design for Test STA Engineer at Tenstorrent, you will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors.

This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs. You will be responsible for defining and implementing the full DFT methodology for our high-speed, multi-core designs, owning the top-level timing constraints and sign-off for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to achieve first-pass silicon success. This role is hybrid, based out of Santa Clara, CA or Austin, TX.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies. , Synopsys PrimeTime, Cadence Tempus etc). Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc.

Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification.

Requirements

across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure. , Scan, JTAG, Memory BIST). , PrimeTime, Tempus etc).

Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs. Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness. Participate in ATE targeted test patterns, validation and silicon- debug Work closely with test and product engineering teams on silicon characterization and validation.