Sr. Engineer, RTL Design AI Hardware

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.

We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Join the team building the silicon behind Tenstorrent’s custom AI platform.

As an RTL Design Engineer, you will contribute to the development of next-generation AI hardware by implementing and optimizing micro-architectures, improving performance and power efficiency, and collaborating across hardware teams. This role offers the opportunity to work on challenging, high-impact designs in a fast-paced environment. This role hybrid, based out of Belgrade, Serbia.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

: An engineer with a strong foundation in digital design and micro-architecture. Familiar with RTL development, debugging, and performance analysis workflows, including clock/reset, power, boot, and debug logic. Comfortable writing Verilog or SystemVerilog and interpreting synthesis and timing results.

Motivated to learn how high-performance AI hardware is built and optimized from the ground up. What We Need: Contributors who can implement and refine micro-architectural features for Tenstorrent’s AI hardware IP. Engineers who can analyze performance bottlenecks and suggest improvements that balance power, area, and frequency.

Teammates who collaborate across RTL, DV, performance, and physical design to explore and evaluate design trade-offs. Developers who can debug RTL issues in both simulation and post-silicon environments and contribute to improving internal tools and flows. What You Will Learn: Techniques for developing high-performance RTL targeting AI and ML workloads.

How power, performance, and area are balanced across design, verification, and physical implementation. Tools and methods used to evaluate design trade-offs and optimize compute architectures. What it takes to ship production-grade silicon that supports next-generation AI systems.

Compensation

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Benefits

, and we are an equal opportunity employer. S. export-controlled technology.

S. S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).

Requirements

S. S. S.

Commerce Department or applicable federal agency. S. export laws, any offer of employment will be rescinded.